1. Field
This disclosure relates to memories and more particularly to mitigating issues that can arise with SRAMs.
2. Description of the Related Art
Static random access memory (SRAM) retains its state as long the circuit remains powered. FIG. 1 illustrates a conventional six transistor SRAM cell 100 in which four transistors 101, 103, 105, and 107, forming two cross-coupled inverters, store the cell value. Negative Bias Temperature Instability (NBTI) as well as Positive Bias Temperature Instability (PBTI) effects results in threshold voltage (Vth) shifts of static random access memory (SRAM) cells when the device is placed under stress. The Bias Temperature Instability (BTI) effects increase the effective threshold voltages of both the n-channel field effect transistors (NFET) and p-channel field effect transistors (PFET) devices in the SRAM cells and makes them ‘weaker’. If the same data is held by the SRAM cell for prolonged periods of time, the threshold voltage of different FETs within the SRAM cell gets affected differently causing asymmetrical behavior of the cross coupled inverters and thereby a degradation of both Static Noise Margin (SNM) as well as cell read currents. The SNM degradation especially causes the low-voltage operations of SRAMs to suffer. FIG. 1 shows the effects of BTI on different transistors within an SRAM cell. NTBI affects PMOS transistors 101 and 105. PBTI stress affects NMOS transistors 103, 107, 109, and 111.